AR# 37648


Spartan-6, DCM_CLKGEN - After changing the M and D via SPI, how long before the LOCK re-asserts?


When I perform a simulation of the DCM_CLKGEN and change the M and D via SPI, the LOCK does not de-assert. Should it? Also, how long should it take to re-assert?


The is an issue in the unisim and simprim models in ISE 12.2 and earlier software.The LOCK does not de-assert after you change the M and D values. This issue is to be fixed in ISE Design Suite12.3.
The correct functionality of the LOCKED signal is described in the Spartan-6 FPGA Clocking Resources User Guide (UG382):
The LOCK re-asserts after PROGDONE has gone High. The length of time for this to occur is specified as LOCK_FX in the Spartan-6 FPGAData Sheet (DS162):



Answer Number 问答标题 问题版本 已解决问题的版本
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 37648
日期 12/15/2012
状态 Active
Type 综合文章
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