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AR# 37752

Design Assistant for PCI Express - Issues in simulation when user inputs are perfectly aligned to trn_clk or user_clk_out

描述

This answer record identifies an issue which occurs when the user inputs are perfectly aligned to trn_clk or user_clk_out (AXI) in simulation.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536).

The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe.

Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

解决方案

When presenting TLPs at the user interface perfectly aligned to the trn_clk or user_clk_out (AXI), you might experience issues. 

Please make sure to slightly delay your data relative to the clock. 

Otherwise, the simulation can fail with otherwise unexplained issues. 

Symptoms of this issue are:

  • TLP received is corrupted
  • trn_fc_ph and trn_fp_nph not behaving correctly

Verilog:

Use something similar to the following:
 

 #1 new_signal =old_signal;


or add a #1 in your always block:
 

always @(posedge user_clk_out)
begin
new_signal = #1 old_signal;
end


VHDL:
Use something similar to the following:


new_signal <= old_signal after 1 ps;


or add "after 1ps" in your process assignment:
 

process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
new_signal <= old_signal after 1 ps;
end process;

 
Revision History:
10/11/2010 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
36749 Design Assistant for PCI Express - Simulation Questions Regarding Transaction Layer Traffic N/A N/A
AR# 37752
日期 03/23/2015
状态 Active
Type 解决方案中心
IP
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