AR# 37817: Design Assistant for PCI Express - How does a Gen 1 endpoint handle the reserved bits in the TS1/TS2 ordered sets that are used in Gen 2?
Design Assistant for PCI Express - How does a Gen 1 endpoint handle the reserved bits in the TS1/TS2 ordered sets that are used in Gen 2?
For Gen 1 PCIe, bit 0 and bits 2:7 of the TS1/TS2 ordered sets were reserved and set to 0. However, these bits are used for Gen 2 PCIe. Do Xilinx cores correctly interpret these bits if in Gen 1 or Gen 2 mode?
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A Gen 1 endpoint such as the Spartan-6 endpoint or Virtex-6 endpoint operating in Gen 1 mode transmits 0b for these bits as required by the specification. If the Gen 1 endpoint is interfacing with a Gen 2 capable device that is transmitting non-zero values for these bits, the Xilinx Gen 1 endpoint correctly ignores these settings.