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AR# 37863

MIG v3.6-v3.7, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error


A MIG GUI issue exists for specific multi-controller designs where the default banks are used and an FF1760 package is targeted:

  • XC6VLX550T-FF1760
  • XC6VLX760-FF1760
  • XC6VLX550TL-FF1760
  • XC6VLX760L-FF1760

The issue is that MIG selects four columns for the Data group in the default bank selections which causes MIG to generate an invalid pin-out.

The following error is seen in MAP:

ERROR:Place:905 - Components driven by Regional clock net <2>> can't be placed and routed because location constraints are causing the clock region rules to be violated.

This issue only occurs in specific scenarios for multi-controller designs; DDR3 SDRAM controller designs with a frequency of 400 MHz or less and memory parts similar to the following:

  • x4 component with data width of 72
  •  x8 component with data width of 144
  • RDIMM whose base part is of x4 with data width of 72

There is no issue for single controller designs.


Three controllers are selected in the GUI, one is a DDR3 controller and the other two are QDRII+ controllers.

For the DDR3 controller, the frequency is 2500 ps and the memory part selected is MT18JSF51272PZ-1G4.

In this case, the data group will be selected across four columns by default and the generated pin-out will be invalid.

Upon implementing the generated design it will fail in MAP.


To work around this issue, re-generate your MIG design and manually select the banks.

You can do this by selecting "Deselect Banks" on the Bank Selection screen and then manually entering the banks.

When the banks are manually selected, the issues do not occur.



Answer Number 问答标题 问题版本 已解决问题的版本
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A


AR# 37863
日期 08/18/2014
状态 Active
Type 已知问题
  • Virtex-6 LXT
  • Virtex-6 LX
  • MIG