AR# 3791: 4.1i CORE Generator - 4K Synchronous FIFO LogiCORE output is only valid when "READ Enable" is enabled
4.1i CORE Generator - 4K Synchronous FIFO LogiCORE output is only valid when "READ Enable" is enabled
Keywords: CORE Generator, COREGen, IFO, full, read enable, READ Enable, RE, single, dual, port
General Description: The CORE Gerator 4K Synchronous FIFO data output does not behave the way some users may expect when RE (READ Enable) is inactive and the FIFO is FULL. The output is actually only valid when RE is enabled.
After all memory locations in the COREGen FIFO are filled and the FULL status output goes high, if WE is still asserted on the next clock cycle, the FIFO output displays the value that was written to it at the first memory location, even though the RE (READ Enable) input was never asserted.
The main aspect of the FIFO's behavior that may be unexpected is the fact that the FIFO only shows valid output when RE (Read Enable) is active. Once RE is disabled, the output can still change at random, even if you are not performing a READ operation.
The CORE Generator RAM-based FIFO was designed to minimize the number of clock cycles required to write valid data to, or read valid data out of, this buffer. Internally, there is a WRITE Counter that points to the address of the next writable address in the buffer, and a READ Counter, which points to the next address location to be read.
In a Single-Port RAM-based FIFO, a mux selects either the WRITE Counter or the READ Counter to provide the address to the memory. The RE input acts as the mux select control signal. The WRITE Counter always points to the next memory location to be written to, to allow the fastest possible WRITE operation.
Once the last FIFO memory location has been written to, the FIFO is now FULL, and the WRITE Counter cycles back to the first memory location. The value stored at this location appears at the output of the FIFO, even though RE is not asserted; this happens because the WRITE Counter is providing the address to the memory (because RE is not asserted).
If WE is still enabled on the next clock cycle, the current contents of the next location will appear at the FIFO output. Of course, the information at this location will not be overwritten, because the FIFO is now FULL.
Since RE has not been asserted, it should not matter what the FIFO output is at that point. If you subsequently assert RE, you should still see the same value at the output. If it is important that the READ output persist beyond when RE is active, you must add an output register to the FIFO output and tie the register's clock enable to RE.
In the case of a Dual Port RAM-based FIFO, there is no mux that selects between the WRITE and READ Counters. The output of the FIFO always reflects the content of the address on the output of the READ Counter. However, the same principle regarding the output of the FIFO being valid only when RE is active still applies.
After all memory locations in the COREGen FIFO are filled and the FULL status output goes high, if WE is still asserted on the next clock cycle, the FIFO output displays the value that was written to it at the first memory location; it does this even though the RE (READ Enable) input was never asserted.
Again, the FIFO outputs are not guaranteed once RE is de-asserted. If you wish to have the last valid output read from the FIFO persist over more than one clock cycle, register the FIFO output, and use the RE signal to control the CE of this additional register.