General Description: How can I instantiate the READBACK symbol in Leonardo using VHDL or verilog?
解决方案
1
--4K devices, VHDL, Readback using CCLK:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity use_readback is port (trig : in std_logic; rip : out std_logic; data: out std_logic; CLK, D_IN: in std_logic; Q: out std_logic); end use_readback;
architecture xilinx of use_readback is
component RDBK port (TRIG: in std_logic; DATA: out std_logic; RIP: out std_logic); end component;
begin
U1: RDBK port map (TRIG => trig, DATA => data, RIP => rip);
-- Sample User Code My_D_Reg: process (CLK, D_IN) begin if (CLK'event and CLK='1') then Q <= D_IN; end if; end process; -- End My_D_Reg
end xilinx;
2
--4K devices, VHDL, Readback using USER Clock:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;
entity use_readback is port (trig : in std_logic; rip : out std_logic; data: out std_logic; CLK, D_IN: in std_logic; READ_CLK : in std_logic; Q: out std_logic); end use_readback;
architecture xilinx of use_readback is
component RDBK port (TRIG: in std_logic; DATA: out std_logic; RIP: out std_logic); end component;
component RDCLK port (I : in std_logic); end component;
begin
U1: RDBK port map (TRIG => trig, DATA => data, RIP => rip); U2: RDCLK port map ( I => READ_CLK);
-- Sample User Code My_D_Reg: process (CLK, D_IN) begin if (CLK'event and CLK='1') then Q <= D_IN; end if; end process; -- End My_D_Reg