We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37934

Soft Error Mitigation Controller v1.1 - Release Notes and Known Issues


This Release Notes and Known Issues Answer Record is for the Soft Error Mitigation Controller first released in ISE Design Suite 12.3, and contains the following information:
  • General Information
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:


General Information

There is currently no support for simulation of the Soft Error Mitigation Controller. Functional and timing simulation of a design including the controller will compile, but the controller will not exit the initialization state. There is no support for partial reconfiguration when using the Soft Error Mitigation Controller. Please see Chapter 9 of the Soft Error Mitigation Controller User Guide (UG764) for further information on unsupported features and limitations.

The Soft Error Mitigation Controller has been verified using production Virtex-6 FPGA devices. Use of this core on Engineering Silicon (ES) devices is not supported due to a silicon errata item regarding "Configuration Readback". The core may not work at all on ES devices, and if it does, its operation may be unreliable. Therefore, this core must not be used in ES silicon for any purpose other than evaluation. If you are using this core on an ES device for evaluation and you encounter a problem, please obtain a production device. For more information, refer to the Virtex-6 FPGA CES Errata at: http://www.xilinx.com/support/documentation/virtex-6.htm#131587.

The following devices are supported by the core for this release:

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6L XC LXT/SXT
New Features
  • None (this is the initial release)
Resolved Issues

  • None (this is the initial release)
Known Issues
(Xilinx Answer 37935) - Soft Error Mitigation Controller v1.1 - After Meeting Timing PAR Reports Hold Violation Upon Running Another Routing Phase
(Xilinx Answer 38130) - Soft Error Mitigation Controller v1.1 - Virtex-6 -1L Speed Grade ICAP Frequency Limited to 60 MHz
(Xilinx Answer 39350) - Soft Error Mitigation - Timing Simulation Error: Warning: /X_FF RECOVERY Low VIOLATION ON RST WITH RESPECT TO CLK

Revision History
11/29/2010 - Added Answer Record 39350
10/05/2010 - Initial Release




AR# 37934
日期 05/20/2012
状态 Active
Type 版本说明
器件 More Less