AR# 37939: Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1
Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1
This article contains issues resolved in theSpartan-6 FPGA Integrated Block v2.1 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.
Default simulation test has been upgraded to include memory and I/O reads and writes.
cfg_msg_* interface ports on Root Port Model now visible
cfg_msg_* ports are now visible at the top level of the Root Port Model delivered with Endpoint product.
Syntax error in VHDL instantiation template
Syntax error in the VHDL instantiation template was corrected.
User non-posted OK signal undriven in VHDL Root Port model
Issue resolved where the User non-posted OK signal was undriven in the VHDL Root Port model, preventing memory read transactions from passing to the User Interface.
ACK Transmission Latency to Large
Issue resolved where the ACK transmission latency was to large, causing Replay timer on connected component trigger, thus generating an error.
Missing simulation test restored
PCIe tests available in older cores / example designs, which were missing in older versions of the S6 core, have been restored .
Class Code Lookup Assistant added
A Class Code Lookup Assistant has been added the GUI, to help determine the Class Code Values to be used.
Revision History 01/18/2012 - Modified format to use a single AR for all known issues and referenced 45702 for all known issues. Any issue that was listed here is now in AR 45702. 10/26/2010 - Added 37595, 38717 10/11/2010 - Added "AXI" designation to title for doc center. 10/05/2010 - Initial Release