AR# 3802


M1.4 CPLD - Timing violation: Slow simulation model produced with the "Use Local Macrocell Feedback" switch


Keywords: Cpld, M1.4, hold, time, simulation, macrocell, feedback, violation

Urgency: Standard


Simulation model created slower than the correct model.

Hold time errors reported when running design at slower clock
rate than reported by the Timing Analyzer. The reported design should have
run at 100Mhz, but gave timing violations at 20Mhz.
The design simulated properly when the "Use Macrocell Feedback" switch
is not being used. The patch referred to below solves this for M1.4.


This problem is fixed in the latest M1.4 CPLD Tools Update
available on the Xilinx support website:
AR# 3802
日期 03/29/2000
状态 Archive
Type 综合文章
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