AR# 38047: 10.1i CPLDfit - Incorrect equation for FDCPE in report file
10.1i CPLDfit - Incorrect equation for FDCPE in report file
There is an incorrect equation for FDCPE in the report file.
In the equation sections of the rpt file (both verilog and vhdl), the order of pins in the instantiation of the FDCPE component does not match the legend at the end of the ".rpt" file. The instantiation has the pin order (Q,D,C,CE,CLR,PRE), while the legend has the order (Q,D,C,CLR,PRE,CE). This is merely a reporting issue; the jedec behaves correctly.