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  1. 赛灵思 - All Programmable
  2. 技术支持
  3. AR# 3807: XACT-CPLD: Listing of all the Fitter patches

AR# 3807

XACT-CPLD: Listing of all the Fitter patches

Description

Keywords: xact, cpld, patches, list, changes, dates, programs,
application

Urgency: Standard

General Description:

This file contains detailed descriptions of all CPLD software patches
available to customers and FAEs. Each patch is available in PC, Sun and
HP versions as appropriate.

Please note that the dates listed in each file description refers to the
date that the file was added to the patch, not the file creation date. The
file version is the version number displayed when the executable name is
entered on the command line.

You should always update ALL OF THE FILES contained in each patch, otherwise
results may be unpredictable.

解决方案

File Name: FITTERPC.ZIP (PC), FITTERSN.TAR.Z (Sun), FITTERHP.TAR.Z (HP)
Last Updated: 4/3/97
Affected Products: XACT-CPLD v6.01 and earlier
XABEL-CPLD v6.12, v6.11, v6.10
Foundation v6.02, v6.01


Affected
Contents Date Ver Products Ver Description

HPLUSAS6.EXE 9/12/96 6.02 XACT-CPLD 6.01 - Corrects internal software error
6.00 occuring when a negative polarity
XABEL-CPLD 6.10 WIRE-AND equation in FastCONNECT
6.11 drives another WIREAND equation.
Foundation 6.01 For example:
/a = b * /c; FC node
d = /a * e; FC node

HITOP.EXE 9/12/96 6.02 XACT-CPLD 6.01 - Eliminates core dump during
6.00 product term assignment
XABEL-CPLD 6.10 optimization
6.11
Foundation 6.01 - Eliminates core dump when
customer trys to mistakenly
drive two output pins from
same logic source. (A logic
function can only drive one
output pin.)

- Supports use of local feedback
path when specified with XACT
Performance and partitioning

- Eliminates incorrect inversion
of signals that used local feed
back path.

- Refined product term assignment
optimization for fitting
efficiency

3/10/97 6.02d XACT-CPLD 6.01 - Added XC9572PC44 support
6.00
XABEL-CPLD 6.10 - Improved error checking to catch
6.11 user pin assignment conflicts
6.12 that would result in incorrect
Foundation 6.01 pinouts being generated in report
file


4/03/97 6.02f XACT-CPLD 6.01 - Eliminates incorrect logic
6.00 implementation that could
XABEL-CPLD 6.10 result in the disabling of
6.11 macrocell feedback. This would
6.12 only occur when the design was
Foundation 6.01 pinlocked and the fitter chose
to insert a buffer between an
output enable controlled logic
funtion and the device pin to
maintain the same pinout.

The fitter will now move the logic
function to a buried macrocell and
insert an output enable controlled
buffer between the logic function
and the pin.

TAENGINE.EXE 7/31/96 XACT-CPLD 6.00 - Corrects incorrect reporting of
XABEL-CPLD 6.10 set_uptime of a clock signal to
itself. Tracing of this false
path makes performance appear
to be slower than it really is.

9/12/96 6.02 XACT-CPLD 6.01 - Rebuilt for consistancy across
6.00 PC, HP and SUN platforms. This
XABEL-CPLD 6.10 file was originally contained
6.11 in TAPC and TASUN patches.
Foundation 6.01

FSIM.EXE 9/12/96 6.02 XACT-CPLD 6.01 - Included in FITTTERHP.TAR only,
6.00 it is included for consistancy
across PC, HP and Sun versions

MODEL6.CHP 8/08/96 XACT-CPLD 6.01 - Correction to XC95216HQ208 and
6.00 XC95180HQ208 package model.
XABEL-CPLD 6.10 Pins 66 and 69 are GND, not I/O.
6.11
Foundation 6.01

11/04/96 XACT-CPLD 6.01 - Added XC9572 JEDEC file
6.00 generation
XABEL-CPLD 6.10
6.11
Foundation 6.01

3/10/97 XACT-CPLD 6.01 - Added XC9572PC44 support
6.00
XABEL-CPLD 6.10
6.11
6.12
Foundation 6.01

HPREP6.EXE 11/04/96 6.02a XACT-CPLD 6.01 - Added XC9572 JEDEC file
6.00 generation
XABEL-CPLD 6.10
6.11 - Corrected ordering of
Foundation 6.01 Usercode bits

3/10/97 6.02c XACT-CPLD 6.01 - Added XC9572PC44
6.00 JEDEC file generation
XABEL-CPLD 6.10
6.11
6.12
Foundation 6.01

4/03/97 6.02e XACT-CPLD 6.01 - Added XC95288 JEDEC
6.00 file generation
XABEL-CPLD 6.10
6.11
6.12
Foundation 6.01

TSIM.EXE 3/10/97 6.02c XACT-CPLD 6.01
6.00
XABEL-CPLD 6.10
6.11
6.12
Foundation 6.01

MODELF.TIM 8/08/96 XACT-CPLD 6.01 - Adjusted
product term clock
6.00 timing for XC95108 -7,-10,-15.
XABEL-CPLD 6.10 The new timing is:
6.11 -7 -10 -15
Foundation 6.01 tPSU (min) 1.5 2.5 4.0
tPH (min) 4.0 4.0 4.0
tPCO (min) 9.5 10.5 12.0

The value of tPTCK in the
timing model is now:
-7 -10 -15
tPTCK (max) 4.0 3.5 2.5

Yes, tPTCK is faster in the
timing model for slower devices.


PARTLIST.XCT 3/10/97 XACT-CPLD 6.01 - Added XC9572PC44 support
6.00
XABEL-CPLD 6.10
6.11
6.12
Foundation 6.01

XC_9500.SDS 3/10/97 XABEL-CPLD 6.10 - Added XC9572PC44 support
6.11
6.12


* Install Instructions *
* *
* Unzip (Untar) files and copy into fitter as follows: *
* *
* For XACT-CPLD *
* For pc : c:\xact9000\data\model6.chp *
* c:\xact9000\data\modelf.tim *
* c:\xact9000\hplusas6.exe *
* c:\xact9000\hitop.exe *
* c:\xact9000\taengine.exe *
* c:\xact9000\tsim.exe *
* c:\xact9000\hprep6.exe *
* For sun : <xact9000>/data/model6.chp *
* <xact9000>/data/modelf.tim *
* <xact9000>/bin/sparc/hplusas6 *
* <xact9000>/bin/sparc/hitop *
* <xact9000>/bin/sparc/tsim *
* <xact9000>/bin/sparc/taengine *
* <xact9000>/bin/sparc/hprep6 *
* For hp : <xact9000>/data/model6.chp *
* <xact9000>/data/modelf.tim *
* <xact9000>/bin/hppahplusas6 *
* <xact9000>/bin/hppa/hitop *
* <xact9000>/bin/hppa/tsim *
* <xact9000>/bin/hppa/fsim *
* <xact9000>/bin/hppa/taengine *
* <xact9000>/bin/hppa/hprep6 *
* *
* For Foundation *
* c:\xact9000\data\model6.chp *
* c:\xact9000\data\modelf.tim *
* c:\xact9000\hplusas6.exe *
* c:\xact9000\hitop.exe *
* c:\xact9000\taengine.exe *
* c:\xact9000\tsim.exe *
* c:\xact9000\hprep6.exe *
* *
* For XABEL-CPLD *
* c:\xabel6\xact9k\data\model6.chp *
* c:\xabel6\xact9k\data\modelf.tim *
* c:\xabel6\xact9k\hplusas6.exe *
* c:\xabel6\xact9k\hitop.exe *
* c:\xabel6\xact9k\hprep6.exe *
* c:\xabel6\xact9k\taengine.exe (XC9K fitter) *
* c:\xabel6\xact9k\tsim *
* c:\xabel6\xact\taengine.exe (XC7K fitter) *
* c:\xabel6\config\xc_9500.sds *
AR# 3807
日期 09/30/2008
状态 Archive
Type 综合文章
的页面