This file contains detailed descriptions of all CPLD software patches available to customers and FAEs. Each patch is available in PC, Sun and HP versions as appropriate.
Please note that the dates listed in each file description refers to the date that the file was added to the patch, not the file creation date. The file version is the version number displayed when the executable name is entered on the command line.
You should always update ALL OF THE FILES contained in each patch, otherwise results may be unpredictable.
File Name: FITTERPC.ZIP (PC), FITTERSN.TAR.Z (Sun), FITTERHP.TAR.Z (HP) Last Updated: 4/3/97 Affected Products: XACT-CPLD v6.01 and earlier XABEL-CPLD v6.12, v6.11, v6.10 Foundation v6.02, v6.01
Affected Contents Date Ver Products Ver Description
HPLUSAS6.EXE 9/12/96 6.02 XACT-CPLD 6.01 - Corrects internal software error 6.00 occuring when a negative polarity XABEL-CPLD 6.10 WIRE-AND equation in FastCONNECT 6.11 drives another WIREAND equation. Foundation 6.01 For example: /a = b * /c; FC node d = /a * e; FC node
HITOP.EXE 9/12/96 6.02 XACT-CPLD 6.01 - Eliminates core dump during 6.00 product term assignment XABEL-CPLD 6.10 optimization 6.11 Foundation 6.01 - Eliminates core dump when customer trys to mistakenly drive two output pins from same logic source. (A logic function can only drive one output pin.)
- Supports use of local feedback path when specified with XACT Performance and partitioning
- Eliminates incorrect inversion of signals that used local feed back path.
- Refined product term assignment optimization for fitting efficiency
3/10/97 6.02d XACT-CPLD 6.01 - Added XC9572PC44 support 6.00 XABEL-CPLD 6.10 - Improved error checking to catch 6.11 user pin assignment conflicts 6.12 that would result in incorrect Foundation 6.01 pinouts being generated in report file
4/03/97 6.02f XACT-CPLD 6.01 - Eliminates incorrect logic 6.00 implementation that could XABEL-CPLD 6.10 result in the disabling of 6.11 macrocell feedback. This would 6.12 only occur when the design was Foundation 6.01 pinlocked and the fitter chose to insert a buffer between an output enable controlled logic funtion and the device pin to maintain the same pinout.
The fitter will now move the logic function to a buried macrocell and insert an output enable controlled buffer between the logic function and the pin.
TAENGINE.EXE 7/31/96 XACT-CPLD 6.00 - Corrects incorrect reporting of XABEL-CPLD 6.10 set_uptime of a clock signal to itself. Tracing of this false path makes performance appear to be slower than it really is.
9/12/96 6.02 XACT-CPLD 6.01 - Rebuilt for consistancy across 6.00 PC, HP and SUN platforms. This XABEL-CPLD 6.10 file was originally contained 6.11 in TAPC and TASUN patches. Foundation 6.01
FSIM.EXE 9/12/96 6.02 XACT-CPLD 6.01 - Included in FITTTERHP.TAR only, 6.00 it is included for consistancy across PC, HP and Sun versions
MODEL6.CHP 8/08/96 XACT-CPLD 6.01 - Correction to XC95216HQ208 and 6.00 XC95180HQ208 package model. XABEL-CPLD 6.10 Pins 66 and 69 are GND, not I/O. 6.11 Foundation 6.01