UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38083

MIG v3.6-v3.61, Virtex-6 DDR3 - Multi-Controller Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16

Description

MIG v3.6-v3.61 Multi-controller DDR3 SDRAM Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16 with the following error:

# -- Compiling module sim_tb_top
# ** Error: ../sim/sim_tb_top.v(1091): Range must be bounded by constant expressions.
# ** Error: ../sim/sim_tb_top.v(1091): Range must be bounded by constant expressions.
# ** Error: ../sim/sim_tb_top.v(1092): Range must be bounded by constant expressions.
# ** Error: ../sim/sim_tb_top.v(1092): Range must be bounded by constant expressions.
# ** Error: /tools/gensys/questa/6.5c/linux_x86_64/vlog failed.

This issue does not exist for any VHDL designs, single controller Verilog designs, or multi-controller Verilog designs that do not target a UDIMM.

解决方案

Thisoccurs becausethe parameter DQ_WIDTH is not being mapped properly to the memory model in the sim_tb_top (testbench) module.

For example, if the design is generated for 2 controllers ("Number of Controllers" option in GUI set to 2) and x16 UDIMM is selected for the second controller, port mapping to the memory model of UDIMM is as follows in the sim_tb_top module.

Existing code:
.dq ({c1_ddr3_dq_sdram[DQ_WIDTH-1:(C1_DQ_WIDTH-8)],
c1_ddr3_dq_sdram[DQ_WIDTH-1:(C1_DQ_WIDTH-8)]}),

Instead, port mapping should be changed as follows.
Modified code:
.dq ({c1_ddr3_dq_sdram[C1_DQ_WIDTH-1:(C1_DQ_WIDTH-8)],
c1_ddr3_dq_sdram[C1_DQ_WIDTH-1:(C1_DQ_WIDTH-8)]}),

The above example properly port maps the DQ_WIDTH parameter when a UDIMM is selected as the second controller. This fix needs to be applied to properly map the DQ_WIDTH parameter for all x16 UDIMM controllers.

This is fixed in the ISE 13.1 MIG v3.7 software release.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
37173 MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
37173 MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A
AR# 38083
创建日期 09/17/2010
Last Updated 05/20/2012
状态 Active
Type 已知问题
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG