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AR# 38158

MIG Virtex-6 - Synchronizing User Controller Interfaces


Is it possible to synchronize two MIG controller user interfaces?

MIG by default generates separate clocking generation and distribution logic (e.g., MMCMs and BUFGs) for each controller. The BUFG-driven clocks used to supply the clocks for internal logic ("CLK" and "CLK_MEM") do not have to be phase-aligned with the clock used to provide the read data capture clock ("CLK_RD_BASE"). For this reason, it is possible to modify the clocking logic RTL in order to have the MMCM of one of the controllers provide CLK and CLK_MEM for both controllers.

This has not been fully tested by Xilinx and should only be done for frequencies at 400 MHz or below, as short term drifting in phase between two clocks from two different MMCMs can occur which the MIG Phase Detector Logic might not be able to compensate for at higher frequencies.


Modify the code such that both controllers receive their CLK and CLK_MEM from one of the infrastructure MMCMs. The read clocks would still need to be supplied separately to the individual controllers because they are individually phase-shifted. The MMCM usage would look similar to the following:

MMCM from controller #1: Supplies CLK, CLK_MEM to both controllers. Supplies CLK to customer logic. Supplies read clock to controller #1
MMCM from controller #2: Supplies read clock to controller #2
AR# 38158
日期 12/15/2012
状态 Active
Type 综合文章
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • MIG
Boards & Kits
  • Virtex-6 FPGA Connectivity Kit
  • Virtex-6 FPGA Embedded Kit
  • Virtex-6 FPGA ML605 Evaluation Kit
  • Virtex-6 FPGA ML623 Characterization Kit