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AR# 38219

FIFO Generator - Why does FIFO Generator core only support free-running write and read clocks?


In theLogiCORE IP FIFO Generator v7.2 User Guide (UG175), it states the following:
"The FIFO Generator is designed to work only with free-running write and read clocks. Xilinx does not recommend controlling the core by manipulating RD_CLK and WR_CLK. If this functionality is required to gate FIFO operation, we recommend using the write enable (WR_EN) and read enable (RD_EN) signals."
Whyare customers not allowedto manipulate those clocks?


Xilinx recommends this because the Status flags (empty, full, Almost Full, Almost Empty,Programmable Full,Programmable empty) will not give the true status of the FIFO for programmable rd_clk and wr_clk.
If an application isrequired to gate FIFO operation, it is recommended that you control the core by using thewrite enable (WR_EN) and read enable (RD_EN) signals, as stated intheLogiCORE IP FIFO Generator v7.2 User Guide (UG175).
AR# 38219
日期 12/15/2012
状态 Active
Type 综合文章
  • ISE - 10.1
  • ISE Design Suite - 11.1
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  • ISE Design Suite - 11.3
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  • FIFO Generator