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AR# 38232

Design Assistant for XST - Help resolving "HDLCompiler:718: Port connections cannot be mixed ordered and named" errors.

Description

Refer to this Answer Record for help resolving "HDLCompiler:718: Port connections cannot be mixed ordered and named" errors.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.

解决方案


This message appears when both ordered and named port connections are used for a module instantiation in Verilog. This is not allowed. An instantiation in Verilog should use either named or ordered connections.

WHAT NEXT:

Modify the instantiations to use either the named connections or ordered connections; in other words, do not mix them.

EXAMPLE:

Consider the following RTL:

module top(i, o);
input i;
output o;
test inst(i, .out(o));
endmodule

module test(in, out);
input in;
output out;
endmodule

In the instantiation of module 'test', two port connections have been used. The first portis ordered connection, the secondis named connection. This is not allowed.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
38927 面向 XST 的 Xilinx 解决方案中心 N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40379 Design Assistant for XST Help understanding the XST report to resolve errors\warnings N/A N/A
AR# 38232
创建日期 09/24/2010
Last Updated 12/15/2012
状态 Active
Type 综合文章