AR# 38249


Logicore 3GPP LTE Turbo Decoder v2.0 - Why do I see MHD_DOUT_WLAST always asserted in hardware but not in simulation


For the Logicore 3GPP LTE Turbo Decoder v2.0 why is the MHD_DOUT_WLAST signal always asserted in hardware, but in simulation it is asserted for just one clock cycle? This one clock cycle representing the last data of a block is currently on the MHD_DOUT port output.


Data sheet DS675 mentions MHD_DOUT_WLAST is only valid when MHD_DOUT_WVALID is high. Therefore, if MHD_DOUT_WLAST stays high for extra cycles this does not indicate the core is operating incorrectly as the MHD_DOUT_WVALID is not high at that time.

The difference between simulation and ChipScope analyzer is caused by the behavior of an SRL based FIFO that is used to buffer the output signals. The FIFO always output data and when the FIFO becomes empty, it will output an old value previously stored within the FIFO. This could be just as likely to be high as low. It will not be valid as it is just a value left in the FIFO from a previous output. .

In simulation, the SRL model will be reset each time the simulation is run (i.e. the SRL will not contain any old data). However, when run in hardware it is unlikely that the device is powered off each time (remember, it is not possible to reset SLR delays in hardware) and, therefore, the outputFIFO may contain a different initial set of data. This is the cause of the difference between simulation and hardware.

Please see (XilinxAnswer 30630) for a detailed list of LogiCORE 3GPP LTE TurboDecoder Release Notes and Known Issues.



Answer Number 问答标题 问题版本 已解决问题的版本
30630 LogiCORE 3GPP LTE Turbo Decoder - Release Notes and Known Issues N/A N/A
AR# 38249
日期 12/15/2012
状态 Archive
Type 综合文章
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