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AR# 38305

12.2 Project Navigator - Hierarchy is not correct for explicit/direct VHDL instantiations using VHDL library

Description

In VHDL, direct instantiations allow the ISE tool to correctly build the hierarchy of the project, such as:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library theand;
use theand.box;
entity top is

Port ( clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (5 downto 0);
dout : out STD_LOGIC_VECTOR (2 downto 0));
end top;
architecture Behavioral of top is
begin
AND_INST: entity theand.box
port map (
A => din(0),
B => din(1),
C => dout(0));
end Behavioral;

However, if inside this direct instantiation we begin to use relative "work." library references, Project Navigator cannot build the project hierarchy correctly.

For instance, imagine that you are compiling the following file into "theand" library:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gate is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end gate;
architecture Behavioral of gate is
begin
C <= A and B;
end Behavioral;

In addition, the following file is compiled to "theand" library, but the reference to the gate entity is performed using "work." as a relative working library, then ISE does not build the project hierarchy correctly:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity box is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end box;
architecture Behavioral of box is
begin
GATE_INST: entity work.gate
port map (
A => A,
B => B,
C => C);
end Behavioral;

解决方案


This occurs for a Virtex-6 or Spartan-6 FPGA (or later device family) project if an entity within a VHDL library other than "work" instantiates an entity or Module in the "work" library.

Example: A verilog module is being instantiated in a VHDL module, and the VHDL module is in a non-work library. The Verilog module is in work because it cannot be assigned to a library. The hierarchy is not shown correctly and when synthesis is run, it fails to properly bind the instantiation. NGDBuide then fails due to the missing module.

To work around this issue:
  1. If possible, move instantiated Entities to a library other than the "work" library.
  2. If it is not possible to move the module to a library (e.g., Verilog module), as a temporary solution in ISE Design Suite 12.2, you can manually modify the PRJ file to change the verilog library to be the same as the VHDL library, and then run XST on a command line. The resulting ".ngc" could be added as the source for a new project, or the implementation flow could be run on command line as well.

In ISE Data Sheet 12.3, the "Library for Verilog Sources" option was added to the "Synthesis - XST" synthesis options.

This option allows a user to specify any of the project VHDL libraries, other than "work," as the library for Verilog sources.

AR# 38305
创建日期 10/05/2010
Last Updated 01/19/2011
状态 Active
Type 已知问题
Tools
  • ISE Design Suite - 12.2