AR# 38319


Design Assistant for V4/V5/V6 FPGA Embedded Tri-Mode Ethernet MAC - Hardware Debug and Link Bring up


This answer record identifies starting points when debugging hardware and link bring up issues to the Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC.

Note: This Answer Record is a part of the Ethernet IP Solution Center (Xilinx Answer 38279).The Xilinx Solution Center for Ethernet IP is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Ethernet IP Solution Center to guide you to the right information.


The Debugging Designs Chapter at the end of the Virtex-6 and Virtex-5 FPGA Embedded TEMAC Wrapper Getting Started Guide has a Hardware debug section with guidance on:
  • General Checks for Hardware Debug
  • Debugging Problems with Transmitting and Receiving Frames
  • Link Bring Up Using 1000BASE-X or SGMII
  • Problems with the MDIO
  • Configuring the Ethernet MAC to the Correct Speed

The Getting Started Guides are available at the below links:



Answer Number 问答标题 问题版本 已解决问题的版本
38279 Ethernet IP 解决方案中心 N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
38281 Ethernet IP Solution Center - Virtex-4/-5/-6 FPGA Embedded Tri-Mode Ethernet MAC Design Assistant N/A N/A
AR# 38319
日期 01/23/2013
状态 Active
Type 综合文章
器件 More Less
People Also Viewed