AR# 38334: BPI Configuration Interface Needs Data on Every A<0> Cycle - A<0> Must be Connected to LSB of Address Bus
BPI Configuration Interface Needs Data on Every A<0> Cycle - A<0> Must be Connected to LSB of Address Bus
The BPI interface in the Xilinx FPGA devices expects data on every CCLK cycle. This can lead to potential problems when using a standard 16-bit BPI interface. Note that you must always connect an A<0> to the flash addresses.
A general 16-bit BPI interface does not use the A<0> pin to address the flash memory. This allows forword addressing instead of byte addressing in 16-bit mode. If you use word addressing,it conflicts with the FPGA BPI configuration interface.
The FPGA BPI interface requires data on every CCLK cycle, and, therefore, with every A<0> cycle. If A<0> is not connected and A<1> is the least significant bit of the address bus,each word will be read twice.
The next table illustrates this point:
This is why A<0> must always be connected to theleast significant bitof the data bus.