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  3. AR# 3833: F1.4 Schematic: How to import and edit a macro without affecting the original source file
  4. AR# 38339: Virtex-6 -1L - Reduction in Configuration Timing Specifications

AR# 38339

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Virtex-6 -1L - Reduction in Configuration Timing Specifications

描述

The Virtex-6 FPGA Data Sheet: DC and Switching Characteristics (DS152 (v2.9) September 20, 2010 and earlier versions) contain timing information for configuration specification. The timing numbers outlined below will be updated in later versions of the Data Sheet. This is based on final characterization for the -1L parts and updates to these specifications will only affect the -1L parts. Only the timing specifications listed in the table below are affected and all other values in the data sheet still hold true.

解决方案


Symbol
Description
Origional Spec
v2.9 and earier
-1L Only
Updated Specs

v3.0 and later

-1L Only

Unit

TPOR
Power-on-reset
55
60
ms, Max

FMCCK
CCLK frequency, serial modes
100
70
MHz, Max

FMCCKTOL
Master CCLK tolerance from nominal
55
60
%, Max

TMCCKL/TMCCKH
Master CCLK low/high duty cycle
45/55
40/60
%, Min/Max

TSMCSCCK
CSI_B setup for SelectMAP/ICAP
4.5
5.5
ns, Min

TSMWCCK
RDWR_B setup for SelectMAP/ICAP
13.5
16
ns, Min

FRBCCK
Readback CCLK frequency for SelectMAP/ICAP
100
60
MHz, Max

FTCK/FTCKB
TCK frequency for configuration/boundary-scan
66
33
MHz, Max
AR# 38339
日期 12/15/2012
状态 Archive
Type 综合文章
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