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AR# 38366

Virtex-6 GTX ES Devices - Glitches in TXOUTCLK

描述

There are glitches observed in TXOUTCLK when the Delay Aligner is used.

After performing Phase Alignment, TXDLYALIGNDISABLE is de-asserted. When TXDLYALIGNDISABLE is de-asserted, TXOUTCLK in some cases has a glitch or is phase-shifted. 

This behavior can also cause the MMCM driven by TXOUTCLK to lose lock and can cause timing violations in the fabric logic.

解决方案

In ES Devices, toggling TXDLYALIGNDISABLE causes a reset to the delay line. When the delay line is thrown into reset by high TXDLYALIGNDISABLE, a deformation of the output clock can result, as the delay line suddenly reverts to its midpoint value. 

Another deformation can occur when TXDLYALIGNDISABLE drops and the delay line returns to the value that was frozen in the Delay Aligner FSM.

As a result, toggling TXDLYALIGNDISABLE results in possible glitches on TXOUTCLK when the delay line is used (POWER_SAVE[4]=0). 


The problem has been fixed in Production Devices. In Production Devices, when the TXDLYALIGNDISABLE is asserted, the delay line is frozen and it does not revert to the midpoint condition.

AR# 38366
日期 06/23/2017
状态 Active
Type 已知问题
器件
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • XAUI
  • CPRI
的页面