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AR# 38385

10G Ethernet IP Design Assistant - Synthesis and Implementation


This answer record identifies starting points when debugging synthesis and implementation related issues to the 10G Ethernet IP..

Note: This Answer Record is a part of the Xilinx Solution Center for Ethernet IP (Xilinx Answer 38279).The Xilinx Solution Center for Ethernet IP is available to address all questions related to Ethernet IP. Whether you are starting a new design with Ethernet IP cores or troubleshooting a problem, use the Solution Center for Ethernet IP to guide you to the right information.


The example design provided with each core in Core Generator comes complete with implementation scripts andUCF constraints. For more details on using these scripts, see the Detailed Example Design section of the Getting Started Guide. If implementation or timing errors are encountered with the core, it is recommended to first try running the example design to see if the failures are seen there. If the failures do not exist in the example design, then differences between the example design and the design in which failures are seen can be compared.

These Guides are available at the below links:

The Debugging Designs Chapter at the end of the XAUI and RXAUI Users Guide has an Implementation and Timing Errors section with further tips on location and timing constraints.

These Guides are available at the below links:



Answer Number 问答标题 问题版本 已解决问题的版本
38279 Ethernet IP 解决方案中心 N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
38343 Ethernet IP 解决方案中心 - 10G Ethernet IP 设计助手 N/A N/A
AR# 38385
日期 12/15/2012
状态 Active
Type 综合文章
  • 10 Gigabit Ethernet Media Access Controller
  • XAUI