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AR# 38399

SPI-4.2 v10.2 - Virtex-6 FPGAs Global Clocking support for source core removed when using static alignment

Description

For Virtex-6 FPGAs, support for global clocking has been removed for the Source core when the receiver Sink core is configured for static alignment.

解决方案

The SPI-4.2 GUI has been updated to not allow this configuration starting in v10.2rev1 of the core.  Instead of using global clocking, regional clocking is recommended for the Source core when the receiver Sink core is configured for static alignment.

 The SPI-4.2 v10.2 rev1 patch is available for download in (Xilinx Answer 38211).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
38211 SPI-4.2 v10.2 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A
AR# 38399
创建日期 10/01/2010
Last Updated 05/23/2014
状态 Archive
Type 综合文章
器件
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • More
  • Virtex-6 HXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 12.3
IP
  • SPI-4 Phase 2 Interface Solutions