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AR# 38400

SPI-4.2 v10.2 - Reduced performance of Virtex-6 FPGA Source core with global clocking when the receiver Sink core is configured with dynamic phase alignment

Description

For Virtex-6 FPGAs, reduced performance is required for the Source core with global clocking when the receiver Sink core is configured with dynamic phase alignment.

解决方案

The new limits are:
- 900 Mbps for -1 and -2 speed grades
- 1 Gbps for -3 speed grades

The SPI-4.2 GUI has been updated starting in v10.2rev1 of the core. Instead of using global clocking, regional clocking is recommended for higher performance. Below is a table with all of the performance numbers for Virtex-6 Source core with dynamic phase alignment:



The SPI-4.2 v10.2 rev1 patch is available for download in (Xilinx Answer 38211).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
38211 SPI-4.2 v10.2 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A
AR# 38400
创建日期 10/01/2010
Last Updated 05/23/2014
状态 Archive
Type 综合文章
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 12.3
IP
  • SPI-4 Phase 2 Interface Solutions