AR# 38441


12.3 EDK, AXI_V6_DDRx - "ERROR:Xst:1672 - TIMEGRP 'TG_clk_rsync_rise' already defined"


When I use multiple AXI_V6_DDRx controllers in a design, the following errors occur:

"ERROR:Xst:1672 - TIMEGRP 'TG_clk_rsync_rise' already defined"
"ERROR:Xst:1489 - Constraint annotation failed."

How do I resolve this issue?


This issue is caused by the constraints embedded in each netlist not being merged correctly by XST.

To work around this issue, follow these steps for an example core named 'axi_v6_ddrx_0':
  1. Change into the projects implementation directory for the core:
    cd implementation/axi_v6_ddrx_0_wrapper
  2. Edit and save the UCF file to uniquify all timegroup and timespec names. This includes all strings that begin with TNM_, TG_, or TS_. Use an text editor search/replace function to replace each with a core-specific version, such as TNM_0, TG_0, and TS_0. Backup this file for later use.
  3. Merge the modified UCF into the NGC netlist file:
    ngcbuild -uc axi_v6_ddrx_0_wrapper.ucf axi_v6_ddrx_0_wrapper.ngc ../axi_v6_ddrx_0_wrapper.ngc
  4. Continue with the XPS build process normally. Any changes to the memory controller parameters or a project clean will require all changes to be remade.

This issue is scheduled to be fixed starting in EDK 13.1 for AXI_V6_DDRx, with additional changes planned in XST for 13.2 as a generic fix for future cores.
AR# 38441
日期 01/18/2011
状态 Active
Type 综合文章
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