We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38452

Virtex-6 GTX Transceiver - DRP Addresses above 0x4Fh might not respond under power-down or reset conditions


Users of the Virtex-6 FPGA GTX Transceiver have the ability to use its DRP interface to read and write from configuration and other memory within the transceiver. Typically, following a read or write, DRDY asserts to indicate the completion of that operation. This answer record discusses situations where DRDY might not assert as expected.


The main body of the DRP memory space of the Virtex-6 FPGA GTXTransceiver extends from 0x00 to 0x42h and will respond to DRP reads and writes without a problem. There are a couple of addresses above 0x42 that are supported (most notably 0x82 for PRBS_ERR_CNT) that might not assert DRDY if the internal clock is not toggling. This situation can occur if either PLL is powered down or held in reset via GTXTX/RXRESET or TX/RXPLLRESET.
AR# 38452
日期 12/15/2012
状态 Active
Type 综合文章
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 HXT