2. You should assert global reset for at least one clock cycle to initialize the entire design. This is a gneral rule for any design that contains flip-flops and/or latches.
3. When RFD goes high, you can then assert the first data. The input data and the ND input must both be stable for some period of time before the data is clocked in on the next rising clock edge. Asserting both ND and data shortly after the falling edge of the clock should ensure that this requirement is met. ND ("New Data") can be asserted (driven high) on the same falling clock edge as the data, and should be asserted for one clock cycle.
4. The state of ND should always be defined, and ND should NEVER be asserted when RFD is low. If this ever occurs, the filter's operation will become undefined for a number of clock cycles. During this period, the behavioral model and the actual filter behavior will not match.
5. The output on the RSLT port will be valid when RDY goes high. You must ignore the output at RSLT at all other times.
6. Due to an issue (CR 103333) with the way full precision output width is calculated, the TRIM EMPTY ROMS options will usually give you a result which is inconsistent with what you may expect.
To avoid this problem, you should allow always direct COREGEN to generate the core with the full precision output bus width. The full precision output width value is noted under the Output Width field in the FIR filter GUI for the specific data and coefficient widths that you specify. However, the field is not pre-set as the default value, so you must manually enter that value in the field. Then simply leave unconnected those output bits that you do not need.
In other words, do not select anything smaller than the full precision value displayed in the GUI for the FIR filter output width..