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AR# 38490

LogiCORE DVB S2 FEC Encoder v2.0- Why do I get incorrect output on the encoder when using Virtex-6 in VHDL simulation?


For LogiCORE DVB S2 FEC Encoder v2.0 I see incorrect data output on the encoder when using Virtex-6 FPGA and doing VHDL simulation regardless of if its unisim or simprims. Why is this?


There is an issue with the IP and doing VHDL simulation. This will manifest itself in the output from the core being incorrect in unism and simprims simulation. The workaround is to use Verilog simulation netlists for unism and simprim testing.

There are no problems with the NGC netlist generated and this will work on hardware.

For a detailed list of LogiCORE DVB S2 FEC Encoder  Release Notes and Known Issues, see(Xilinx Answer 30173).



Answer Number 问答标题 问题版本 已解决问题的版本
30173 LogiCORE IP DVB-S2 FEC Encoder - Release Notes and Known Issues N/A N/A
AR# 38490
日期 05/26/2014
状态 Archive
Type 综合文章
  • DVB-S.2 FEC Encoder