AR# 38495: LogiCORE IP Video On Screen Display v1.0 - Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?
AR# 38495
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LogiCORE IP Video On Screen Display v1.0 - Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6?
描述
Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?
解决方案
This is a known problem that only affects the pCore interface and is addressed in the next release of the Video On Screen Display IP.
This problem has been fixed in the Video On Screen Display 1.0 rev1 patch. See (Xilinx Answer 35635) to obtain the patch.
Please see (Xilinx Answer 33257) for a detailed list of LogiCORE IP Video On Screen Display Release Notes and Known Issues.