UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变. 智能.
  2. 技术支持
  3. AR# 38524: MIG Spartan-6 - Debug signals are only added to first port in the user interface

AR# 38524

MIG Spartan-6 - Debug signals are only added to first port in the user interface

描述

When creating a MIG design with more than one user port with "Debug Signal for Memory Controller" enabled, the read and write debug signals are only added to the first port, even if that port is unidirectional. 

This means that it is possible to map the read debug signals to a port that only supports write and vice versa.

 For example, if you select P2 for write, and P3 for read, the read and write debug signals are only added to port P2 which means that the read debug signals have no driver since port P2 supports only supports writes.  


解决方案

In order to map debug signals correctly when the first user port is unidirectional, you need to modify the example_top.v or example_top.vhd file and modify where the debug signals are mapped. 

If the first port is read only, the write debug signals should not be mapped to that port but to the next port that supports writes.

If the first port is write only, the read debug signals should not be mapped to that port but to the next port that supports reads.  

Below is an example for corrected VHDL where user port 2 is set to write and user port 3 is set to read. 

The incorrect mapping is commented out.

gen_dbg_enable:if (DEBUG_EN = 1) generate
     -- controller 1
     c1_dbg_data(255 downto 0) <= ( c1_zeroes1 &
         c1_cmp_error &
         c1_cmp_data &
                              c1_cmp_data_valid & 
         c1_p2_cmd_en &
         c1_p2_cmd_instr &
         c1_p2_cmd_bl &
         c1_p2_cmd_byte_addr &
         c1_p2_cmd_empty &
         c1_p2_cmd_full &

--         c1_p2_rd_en &
--         c1_p2_rd_data(31 downto 0) &
--         c1_p2_rd_full &
--         c1_p2_rd_empty &
--         c1_p2_rd_count &
--         c1_p2_rd_overflow &
--         c1_p2_rd_error &

         c1_p3_rd_en &
         c1_p3_rd_data(31 downto 0) &
         c1_p3_rd_full &
         c1_p3_rd_empty &
         c1_p3_rd_count &
         c1_p3_rd_overflow &
         c1_p3_rd_error &

         c1_p2_wr_en &
         c1_p2_wr_mask(3 downto 0) &
         c1_p2_wr_data(31 downto 0) &
         c1_p2_wr_full &
         c1_p2_wr_empty &
         c1_p2_wr_count &
         c1_p2_wr_underrun &
         c1_p2_wr_error
    );



In addition, the signal names in the example_top.cdc file need to be changed to reflect the new mapping. 

So c1_p2_rd_en needs to be replaced with c1_p3_rd_en etc.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 38524
日期 12/04/2014
状态 Active
Type 综合文章
器件
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG
的页面