AR# 38547: Virtex-5 Architecture Wizard - Out of range PFD allowed, resulting in DRC error
AR# 38547
Virtex-5 Architecture Wizard - Out of range PFD allowed, resulting in DRC error
Description
The Virtex-5 Architecture Wizard allows PLL values that violate the minimum or maximum Phase Frequency Detector (PFD) input frequency. This causes a DRC error or warning to be issued by the implementation tools.
解决方案
Example:
Architecture Wizard is used to generate a PLL with the following values:
Architecture Wizard incorrectly allows generation of this configuration.
During implementation, a DRC error or warning will occur:
WARNING:PhysDesignRules:2236 - The DIVCLK_DIVIDE value 5 of PLL_ADV instance Clocking/clk18p8/PLL_ADV_INST is above the Fin / Fpfd value 2.631579, where Fin is the input frequency, 50.000000 MHz, and Fpfd min - max values of 19.000000 - 450.000000 MHz.
The valid ranges at the phase frequency detector are between 19 MHz and 450 MHz (Fpfdmin and Fpfdmax).
The 2.613579 comes from the input rate of 50 MHz divided by the 19 Mhz. The DRC message is valid.
Workaround:
Use valid DIVCLK_DIVIDE values such that the Fpfdmin and Fpfdmax specifications from the Virtex-5 FPGA Data Sheet are not violated.