We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3863

3.1i CORE Generator - How do I generate Foundation functional simulation files for a VHDL design?


Keywords: CORE Generator, COREGen, Foundation, functional, simulation, VHDL, .alr, 2.1i, 1.5, 1.4

Urgency: Hot

General Description:
Simulating a VHDL design with the Foundation simulator requires that a Foundation simulation netlist (.alr) file be generated for the design. How do I do this?


In the 1.5 and 1.4 versions of CORE Generator software, if you are using a top-level VHDL file in Foundation and wish to perform a pre-NGDBuild functional simulation, the only way to generate the required .alr file for the COREGen module is to include "Foundation Schematic Symbol" as one of your output formats when you set "Output Options."

This is because the same Foundation executable currently generates both the schematic symbol and the .alr functional simulation model for the core.

To obtain the .alr file for your core in the 2.1i and 3.1i releases, simply select "VHDL" for your Design Flow setting, and "Foundation" as your vendor if you are running CORE Generator in stand-alone mode.

Additional information on the Foundation VHDL flow can be found
in the online CORE Generator User Guide, which is accessible
from the Help menu.
AR# 3863
日期 08/23/2002
状态 Archive
Type 综合文章