When I use integrated MIG flow in EDK design andselect thesingle-end clockoption in the MIG GUI, it finishes the flow successfully, however, it reports the following error while generating bitstream:
"ERROR:EDK:3900 - issued from TCL procedure"::hw_mpmc_v6_02_a::syslevel_drc_mig_flow" line 88 C_USE_MIG_FLOW (IPNAME:mpmc, INSTANCE:DDR2) - There have been changes to this design that have changed the number of external memory pins"
How do I resolve this error?
Choosing the single clock setting in the MIG GUI generates a UCF file that is different than the one that is generated automatically by platgen. The MIG GUI UCF keeps the unusedidly_clk_200pin, whileplatgen removes it, and the difference in pinouts triggers this DRC error.
The current work-around is to not choose the single-clock option, use standalone MIG flow, or to manually comment out theidly_clk_200 in the _xps/mig/gui/ directory.
This issue is fixed for Virtex-6 only starting in EDK 13.1. However, it is not currently planned to be resolved for Spartan-3, Virtex-4, and Virtex-5 FPGA families.