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AR# 38690

12.3 EDK - New XBD format for Base System Builder

Description

The following describes the details surrounding the new XBD format.

解决方案

XBD2

The Xilinx Base Description (XBD) file defines the supported interfaces of a given board, system, or sub-system. XBD enables designers to create a system-level design through EDK's Base System Builder (BSB), even though they might not know how to read a board schematic or make pin constraint assignments. The following information is included for a given board: FPGA arch/family/speed grade, I/O list, I/O configuration and peripheral constraints.

BSB reads IP-XACT natively when targeting AXI designs. The IP-XACT based board file set is referenced as XBD2. XBD2 models the FPGA device in IP-XACT as a component XML description which defines the interfaces available on the board. This easily allows designers familiar with IP-XACT to define a data driven mechanism leveraging BSB's system knowledge to assemble designs.

For board designers not familiar with IP-XACT, the board description can be captured in an ASCII text file similar to the MPD format defined to capture a pcore description. This MPD file is known as the Board-MPD. The user is provided a translation tool, MPDX, which generates the IP-XACT files on disk for BSB's repository.

Constraints are captured in a CSV file and a Tcl file which is provided by the user. The CSV file is provided to capture pin constraints and the Tcl is provided to capture more complex constraints like timing constraints.

NOTE: Throughout the document, any reference to Board-MPD is to be considered the input to MPDX translation tool, and reference to XBD2 (IP-XACT) is to be considered the output of MPDX.

Table 1 defines the migration of XBD IO_INTERFACE definitions to IP-XACT busDefinition XML equivalents. All XBD2 component XML files will reference busDefinitions outlined in this table.

Table 1- IO_INTERFACES

XBD Feature IOTYPE XBD2 IP-XACT Equivalent Comments
XIL_CLOCK_V1 xilinx.com|bsb_lib.rtl_busdefs|clock|1.0 Clock
XIL_RESET_V1 xilinx.com|bsb_lib.rtl_busdefs|reset|1.0 Reset
XIL_TEMAC_V1 xilinx.com|bsb_lib.rtl_busdefs|gmii|1.0 GMII
XIL_IIC_V1 xilinx.com|bsb_lib.rtl_busdefs|i2c|1.0 IIC
XIL_MEMORY_V1 xilinx.com|bsb_lib.rtl_busdefs|ddr3_sdram|1.0 DDR3 SDRAM
XIL_MEMORY_V1 xilinx.com|bsb_lib.rtl_busdefs|ddr2_sdram|1.0 DDR2 SDRAM
XIL_PCI_ARBITER_V1 PCI - arbitration_group - not supported
XIL_PCI32_V1 PCI - not supported
XIL_PCIE_V1 PCI Express - not supported
XIL_CPUDEBUG_V1 JTAG - not supported
XIL_TRACE_V1 N/A
XIL_ETHERNET_V1 xilinx.com|bsb_lib.rtl_busdefs|mii|1.0 MII
XIL_GPIO_V1 xilinx.com|bsb_lib.rtl_busdefs|gpio|1.0 GPIO
XIL_EMC_V1 xilinx.com|bsb_lib.rtl_busdefs|flash_nor|1.0 NOR flash
XIL_PS2_V1 N/A
XIL_SPI_V1 xilinx.com|bsb_lib.rtl_busdefs|spi|1.0
XIL_SYSACE_V1 xilinx.com|bsb_lib.rtl_busdefs|sysace|1.0
XIL_TFT_V1 N/A
XIL_UART_V1 xilinx.com|bsb_lib.rtl_busdefs|uart|1.0 UART


The XBD2 file contains a number of spirit:busInterface elements, each corresponding to a hardware module on the board. The type of the module is specified using the VLNV reference of the spirit:busDefinition. The VLNV string is used to match an IP that can communicate with this module.

Table 1 defines VLNV reference in V|L|N|V formatting. The "V" refers to the spirit:vendor which specifies the name of the vendor. The "L" refers to the spirit:library which specifies the vendor's library catalog. The "N" refers to the spirit:name specifies which represents the name of the board. The final "V" refers to the spirit:version which specifies the revision number.

1.1 MPDX

Given a Board MPD input file, mpdx generates the IP-XACT equivalent repository files for BSB.

BSB requires two IP-XACT files to capture the design requirements. One file is the RTL description of the IO interfaces which capture the port direction, port width, and port names. The RTL file is named as <board>.xml. Here is the command-line to generate the file:

% mpdx -mpd_data board -ipx_data rtl board.mpd

The other file is BSB_Component.xml which captures a high-level representation of the system. Here is the command-line to generate the file:

% mpdx -mpd_data board -ipx_data hurri board.mpd

1.2 Board MPD

The following are detailed descriptions and examples of each element in the Board MPD.

On parameters and ports, a logical to physical mapping is defined with the IO_IS and IO_IF tags. The mapping names can be observed from the IP-XACT description of the high level components. The names for parameters pattern a naming convention of <interfaceName>_paramName, and ports pattern <interfaceName>_portName. The tag IO_IF follows a pattern of <interfaceName>. The IO_IS is taken from the spirit:id defined for the parameter within the high level component. The high level IP-XACT component files reside at $XILINX_EDK/data/wizards/ipxact/hurri/xilinx.com/components/.

1.3 Board Options

This defines the VLNV reference in "V|L|N|V" formatting.
  • "V" refers to the spirit:vendor which specifies the name of the vendor. Tools use this element to sort various board files based on vendor name.
  • "L" refers to the spirit:library which specifies the vendor's library catalog.
  • "N" refers to the spirit:name specifies which represents the name of the board. This is the name the tools display for you when they select a board.
  • "V" refers to the spirit:version which specifies the revision number of the board that the XBD2 file represents.

Following is an example:

OPTION VLNV = xilinx.com|bsb_lib.boards|sp605|C


1.4 Reference clock

IO_INTERFACE IO_IF = gclk, IO_TYPE = xilinx.com|bsb_lib.rtl_busdefs|clock|1.0
PARAMETER refclk_frequency_0 = 200000000, DT = LONG, ASSIGNMENT=CONSTANT, IO_IF = clock_0, IO_IS = frequency
PORT GCLK = "", DIR = I, IO_IF = gclk, IO_IS = CLK, SIGIS=CLK, ASSIGNMENT=REQUIRE

1.5 Reference reset

IO_INTERFACE IO_IF = rst_1, IO_TYPE = xilinx.com|bsb_lib.rtl_busdefs|reset|1.0
PARAMETER reset_polarity = 1, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = reset_0, IO_IS = RST_POLARITY
PORT RESET_N = "", DIR = I, IO_IF = rst_1, IO_IS = RESET, SIGIS=RST, ASSIGNMENT=REQUIRE

1.6 UART

IO_INTERFACE IO_IF = RS232_Uart_1, IO_TYPE = xilinx.com|bsb_lib.rtl_busdefs|uart|1.0
PORT RS232_Uart_1_sout = "", DIR = O, IO_IF = RS232_Uart_1, IO_IS = sout
PORT RS232_Uart_1_sin = "", DIR = I, IO_IF = RS232_Uart_1, IO_IS = sin

1.7 GPIO

IO_INTERFACE IO_IF = DIP_Switches_8Bits, IO_TYPE = xilinx.com|bsb_lib.rtl_busdefs|gpio|1.0
PARAMETER DIP_Switches_8Bits_GPIO_WIDTH_ID = 8, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = DIP_Switches_8Bits, IO_IS = C_GPIO_WIDTH
PARAMETER DIP_Switches_4Bits_ALL_INPUTS_ID = 1, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = DIP_Switches_8Bits, IO_IS = C_ALL_INPUTS
PARAMETER DIP_Switches_4Bits_IS_DUAL_ID = 0, DT = STRING, IO_IF = DIP_Switches_4Bits, IO_IS = C_IS_DUAL

PORT DIP_Switches_8Bits_TRI_I = "", DIR = I, VEC = [7:0], IO_IF = DIP_Switches_8Bits, IO_IS = TRI_I

1.8 DDR2 SDRAM

IO_INTERFACE IO_IF = MCB_DDR2, IO_TYPE = xilinx.com|bsb_lib.rtl_busdefs|ddr2_sdram|1.0

PARAMETER C_MEM_PARTNO_ID = EDE1116AXXX-8E, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_PARTNO
PARAMETER C_BYPASS_CORE_UCF_ID = 0, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_BYPASS_CORE_UCF
PARAMETER C_MEM_TRAS_ID = 45000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_TRAS
PARAMETER C_MEM_TRCD_ID = 12500, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_TRCD
PARAMETER C_MEM_TRFC_ID = 127500, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_TRFC
PARAMETER C_MEM_TRP_ID = 12500, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_TRP
PARAMETER C_MEM_TRP_ID = 12500, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_TRP
PARAMETER C_MEM_TYPE_ID = DDR2, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_TYPE
PARAMETER C_MEM_BURST_LEN_ID = 4, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_BURST_LEN
PARAMETER C_MEM_CAS_LATENCY_ID = 5, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_CAS_LATENCY
PARAMETER C_MEM_DDR2_RTT_ID = 50OHMS, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_DDR2_RTT
PARAMETER C_MEM_DDR2_DIFF_DQS_EN_ID = YES, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MEM_DDR2_DIFF_DQS_EN
PARAMETER C_MCB_RZQ_LOC_ID = L6, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MCB_RZQ_LOCPARAMETER C_MCB_ZIO_LOC_ID = C2, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = C_MCB_ZIO_LOCPARAMETER MEMORY_0_BASEADDR_ID = 0x00000000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = MEMORY_0_BASEADDR
PARAMETER MEMORY_0_HIGHADDR_ID = 0x07ffffff, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = MCB_DDR2, IO_IS = MEMORY_0_HIGHADDR

PORT mcbx_dram_clk = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = clk
PORT mcbx_dram_clk_n = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = clk_n
PORT mcbx_dram_cke = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = cke
PORT mcbx_dram_odt = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = odt
PORT mcbx_dram_ras_n = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = ras_n
PORT mcbx_dram_cas_n = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = cas_n
PORT mcbx_dram_we_n = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = we_n
PORT mcbx_dram_ldm = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = ldm
PORT mcbx_dram_udm = "", DIR = I, IO_IF = MCB_DDR2, IO_IS = udm
PORT mcbx_dram_ba = "", DIR = I, VEC = [2:0], IO_IF = MCB_DDR2, IO_IS = ba
PORT mcbx_dram_addr = "", DIR = I, VEC = [12:0], IO_IF = MCB_DDR2, IO_IS = addr
PORT mcbx_dram_dq = "", DIR = IO, VEC = [15:0], IO_IF = MCB_DDR2, IO_IS = dq
PORT mcbx_dram_dqs = "", DIR = IO, IO_IF = MCB_DDR2, IO_IS = dqs
PORT mcbx_dram_dqs_n = "", DIR = IO, IO_IF = MCB_DDR2, IO_IS = dqs_n
PORT mcbx_dram_udqs = "", DIR = IO, IO_IF = MCB_DDR2, IO_IS = udqs
PORT mcbx_dram_udqs_n = "", DIR = IO, IO_IF = MCB_DDR2, IO_IS = udqs_n
PORT rzq = "", DIR = IO, IO_IF = MCB_DDR2, IO_IS = rzq
PORT zio = "", DIR = IO, IO_IF = MCB_DDR2, IO_IS = zio

1.9 NOR FLASH

IO_INTERFACE IO_IF = Linear_Flash, IO_TYPE = xilinx.com|bsb_lib.rtl_busdefs|flash_nor|1.0

PARAMETER Linear_Flash_PHY_TYPE_0 = Linear Flash, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = PHY_TYPE
PARAMETER Linear_Flash_MEM_WIDTH_0 = 16, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = MEM_WIDTH
PARAMETER Linear_Flash_MEM_SIZE_0 = 33554432, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = MEM_SIZE
PARAMETER Linear_Flash_TCEDV_PS_0 = 130000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = TCEDV_PS
PARAMETER Linear_Flash_TAVDV_PS_0 = 130000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = TAVDV_PS
PARAMETER Linear_Flash_THZCE_PS_0 = 35000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = THZCE_PS
PARAMETER Linear_Flash_THZOE_PS_0 = 7000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = THZOE_PS
PARAMETER Linear_Flash_TWC_PS_0 = 13000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = TWC_PS
PARAMETER Linear_Flash_TWP_PS_0 = 70000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = TWP_PS
PARAMETER Linear_Flash_TLZWE_PS_0 = 35000, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = TLZWE_PS
PARAMETER Linear_Flash_EXCLUSIVE = SPI_FLASH, DT = STRING, ASSIGNMENT=CONSTANT, IO_IF = Linear_Flash, IO_IS = EXCLUSIVE

PORT Linear_Flash_address = "", DIR = O, VEC = [0:23], IO_IF = Linear_Flash, IO_IS = address
PORT Linear_Flash_data = "", DIR = IO, VEC = [0:15], IO_IF = Linear_Flash, IO_IS = data
PORT Linear_Flash_ce_n = "", DIR = O, IO_IF = Linear_Flash, IO_IS = ce_n
PORT Linear_Flash_oe_n = "", DIR = O, IO_IF = Linear_Flash, IO_IS = oe_n
PORT Linear_Flash_we_n = "", DIR = O, IO_IF = Linear_Flash, IO_IS = we_n
PORT Linear_Flash_reset = "", DIR = O, IO_IF = Linear_Flash, IO_IS = reset
PORT Linear_Flash_adv_n = "", DIR = O, IO_IF = Linear_Flash, IO_IS = adv_n

2. Define constraints

Constraints are captured in a CSV file and a Tcl file which is provided by the user. The CSV file is provided to capture pin constraints and the Tcl is provided to capture more complex constraints like timing constraints. The name of the CSV is <board>_pins.csv and the name of the Tcl is <board>.tcl.

XBD2 Constraint specification is done with TGI calls to IP-XACT data model that explores the topology of the design. Pin location constraints are associated with the spirit:port element within the spirit:model capture of component XML. Constraints are delivered in UCF format.

2.1 Constraint Delivery model





2.2 CSV Pin file

Many designers use Excel at some stage of an FPGA design to capture pin location. The BSB framework uses the following as a standard. The CVS defines 2 mandatory columns: "Pin Name", and "Pin Index". The other columns like "LOC" are optional. Thus, additional pin properties can be added or removed by simply adding or removing a column. The "Pin Name" must match the name used in the Board MPD file.

Pin Name,Pin Index,LOC,DRIVE,IOSTANDARD,SLEW,TIG

CLK_P,,K15,,,,
CLK_N,,K16,,,,
RESET,,N4,,,,TIG
RS232_Uart_1_sout,,L12,,,,
RS232_Uart_1_sin,,K14,,,,
RS232_Uart_1_ctsN,,U10,,,,
RS232_Uart_1_rtsN,,T5,,,,
DIP_Switches_4Bits_TRI_I,0,D14,,LVCMOS25,,
DIP_Switches_4Bits_TRI_I,1,E12,,LVCMOS25,,
DIP_Switches_4Bits_TRI_I,2,F12,,LVCMOS25,,
DIP_Switches_4Bits_TRI_I,3,V13,,LVCMOS25,,

2.3 TCL

Currently, the BSB framework supports TGI calls through Tcl. TGI calls are defined within the IP-XACT 1.4 documentation.

Tcl and ConstraintMan

bsb:defineAttribute { strPinName strAttName strAttValue }

bsb:addRawUcf { strUcf }

2.3.1.1 Example

An example of how to use the CSV pin file in a script follows:

# nCHandle is instance pointer of ConstraintManager
# nComIdXbd is the SP605
# nDesignID is the HURRI design

proc RunUcfConstraintGen { nCHandle nComIdXbd nDesignId } {
set nResult 0

if { $nCHandle eq "" } {
return $nResult
}

if { $nComIdXbd eq "" } {
return $nResult
}

if { $nDesignId eq "" } {
return $nResult
}

set bApiStatus [ tgi::init "1.0" "fail" "Client connected" ]
if { $bApiStatus == 0 } {
return 1
}

# Repository path
set strRepoDirPath [ bsb::getRepoDirPath $nCHandle ]

# Pin Constraints
set strCsvFilePath [ file join $strRepoDirPath "sp605_pins.csv" ]
set nResult [ \
bsb::registerPinData $nCHandle $nComIdXbd $nDesignId $strCsvFilePath \
]

if { $nResult != 0 } {
return $nResult
}

return $nResult

}

3. Demo Steps

This demonstration is run using the example Board MPD, sp605.mpd, sp605_pins.csv, and sp605.tcl.

Generate board IP-XACT file.
% mpdx -mpd_data board -ipx_data rtl sp605.mpd

Generate BSB_Component IP-XACT file.
% mpdx -mpd_data board -ipx_data hurri sp605.mpd

Copy BSB_Component.xml. sp605.xml, sp605_pins.csv, and sp605.tcl to the IPXACT board area under EDK installment, for example, $XILINX_EDK/board/Xilinx/ipxact/sp605_v1_0/data

Alternatively, copy these files to the EDK project area. For example: <project_directory>/boards/sp605/data.

Following is a link to some example files:
ar38690_example_files.zip

Constraints are captured in a CSV file and a Tcl file which is provided by the user. The CSV file is provided to capture pin constraints and the Tcl is provided to capture more complex constraints like timing constraints. The name of the CSV is <board>_pins.csv and the name of the Tcl is <board>.tcl.XBD2 Constraint specification is done with TGI calls to IP-XACT data model that explores the topology of the design. Pin location constraints are associated with the spirit:port element within the spirit:model capture of component XML. Constraints are delivered in UCF format.Many designers use Excel at some stage of an FPGA design to capture pin location. The BSB framework uses the following as a standard. The CVS defines 2 mandatory columns: "Pin Name", and "Pin Index". The other columns like "LOC" are optional. Thus additional pin properties can be added or removed by simply adding or removing a column. The "Pin Name" must match the name used in the Board MPD file.

CLK_P,,K15,,,,
CLK_N,,K16,,,,
RESET,,N4,,,,TIG
RS232_Uart_1_sout,,L12,,,,
RS232_Uart_1_sin,,K14,,,,
RS232_Uart_1_ctsN,,U10,,,,
RS232_Uart_1_rtsN,,T5,,,,
DIP_Switches_4Bits_TRI_I,0,D14,,LVCMOS25,,
DIP_Switches_4Bits_TRI_I,1,E12,,LVCMOS25,,
DIP_Switches_4Bits_TRI_I,2,F12,,LVCMOS25,,
DIP_Switches_4Bits_TRI_I,3,V13,,LVCMOS25,,

Currently, the BSB framework supports TGI calls through Tcl. TGI calls are defined within the IP-XACT 1.4 documentation.

An example of how to use the CSV pin file in a script follows:

# nCHandle is instance pointer of ConstraintManager
# nComIdXbd is the SP605
# nDesignID is the HURRI design

proc RunUcfConstraintGen { nCHandle nComIdXbd nDesignId } {

set nResult 0



if { $nCHandle eq "" } {
return $nResult}

if { $nComIdXbd eq "" } {
return $nResult }

if { $nDesignId eq "" } {
return $nResult }
set bApiStatus [ tgi::init "1.0" "fail" "Client connected" ]

if { $bApiStatus == 0 } {
return 1 }

# Repository path
set strRepoDirPath [ bsb::getRepoDirPath $nCHandle ]

# Pin Constraints
set strCsvFilePath [ file join $strRepoDirPath "sp605_pins.csv" ]
set nResult [ \ bsb::registerPinData $nCHandle $nComIdXbd $nDesignId $strCsvFilePath \ ]

if { $nResult != 0 } {
return $nResult }
return $nResult}

This demonstration is run using the example Board MPD, sp605.mpd, sp605_pins.csv, and sp605.tcl.

Generate board IP-XACT file.

% mpdx -mpd_data board -ipx_data rtl sp605.mpd

Generate BSB_Component IP-XACT file.

% mpdx -mpd_data board -ipx_data hurri sp605.mpd

Copy BSB_Component.xml. sp605.xml, sp605_pins.csv, and sp605.tcl to the IPXACT board area under EDK installment. For example: $XILINX_EDK/board/Xilinx/ipxact/sp605_v1_0/data

Alternatively, copy these files to the EDK project area, for example, <project_directory>/boards/sp605/data

Following is a link to some example files:
ar38690_example_files.zip

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
34609 12.x EDK - 主要问答记录列表 N/A N/A
AR# 38690
创建日期 10/25/2010
Last Updated 03/05/2013
状态 Active
Type 综合文章
Tools
  • EDK - 12.3