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AR# 38731

MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design

Description

In Virtex-6 MIG DDR3  v3.5-91, when you select the parameter SIM_BYPASS_INIT_CAL = "FAST", it speeds up the simulation of the Example Design and it calibrates error free.

However when you select SIM_BYPASS_INIT_CAL = "SKIP", an error is received and simulation stops.

解决方案

When you select SIM_BYPASS_INIT_CAL = "SKIP", bit alignment errors can occur in the PHY.

As a result the data valid signal is incorrectly asserted with a latency of one clock cycle.

This is scheduled to be fixed in the 14.2 release,  until then ensure that you set the SIM_BYPASS_INIT_CAL parameter to "FAST".

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AR# 38731
创建日期 02/08/2011
Last Updated 08/20/2014
状态 Active
Type 已知问题
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG