AR# 38817: 12.4 EDK, XPS_SYSMON_ADC - Timing fails due to SYSMON component switching errors when PLB_CLK > 80 MHz
AR# 38817
12.4 EDK, XPS_SYSMON_ADC - Timing fails due to SYSMON component switching errors when PLB_CLK > 80 MHz
Description
When using the XPS SYSMON ADC Core for a Virtex-6 FPGA starting in EDK 12.4, the following error occurs: Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:5000) REAL time: 3 mins 30 sec
Timing Score: 5000 (Setup: 0, Hold: 0, Component Switching Limit: 5000 WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. 2 constraints not met. Timing: Completed - 4 errors found.
ERROR: 13 constraints not met.
PAR could not meet all timing constraints. A bitstream will not be generated.
To disable the PAR timing check: 1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.
OR
2> Type following at the XPS prompt: XPS% xset enable_par_timing_error 0
How do I resolve this issue?
解决方案
Starting with ISE Design Suite 12.4, the Virtex-6 System Monitor block is now limited to 80 MHz. If an xps_sysmon_adc IP block is connected to a PLB bus running faster than 80 MHz, the 12.4 tools generate a component switching limit timing violation. To resolve this for a 100 MHz PLB bus system, a second lower frequency bus will be added as follows:
1-Add a second PLB bus.
2-Using the Clock Wizard, connect a 50 MHz clock to the second PLB bus.
3-In the Clock Wizard, use the "Set Clock Relationships?" button to group the 50 MHz clock with the 100 MHz PLB clock (MicroBlaze clock).
4-Add a PLB to PLB Bridge.
5-On the PLB to PLB Bridge, connect the MPLB to the second PLB bus; connect the SPLB to the main PLB bus.
6-Configure the PLB to PLB Bridge: Set the SPLB "Bus Clock Ratio" to 2. This allows the second PLB bus to run at a 1:2 ratio of the main PLB bus speed.
7-Connect the 50 MHz clock to both the System Monitor IP and the second PLB bus.
8-Connect the system reset to the second PLB bus.
9-Connect the Processor System Reset "Slowest_sync_clk" to the 50 MHz clock.
10-Set the address ranges for the PLB to PLB Bridge; all other addresses can remain the same. The PLB to PLB Bridge parameters, "C_RNG0_BASEADDR" and "C_RNG0_HIGHADDR", should match the xps_sysmon_adc address range. Below are the address ranges used in the 12.4 ML605 BIST design from the MHS file: