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AR# 38817

12.4 EDK, XPS_SYSMON_ADC - Timing fails due to SYSMON component switching errors when PLB_CLK > 80 MHz

Description


When using the XPS SYSMON ADC Core for a Virtex-6 FPGA starting in EDK 12.4, the following error occurs:

Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:5000) REAL time: 3 mins 30 sec


Timing Score: 5000 (Setup: 0, Hold: 0, Component Switching Limit: 5000
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
2 constraints not met.

Timing: Completed - 4 errors found.

ERROR: 13 constraints not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:
1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0

How do I resolve this issue?

解决方案


Starting with ISE Design Suite 12.4, the Virtex-6 System Monitor block is now limited to 80 MHz. If an xps_sysmon_adc IP block is connected to a PLB bus running faster than 80 MHz, the 12.4 tools generate a component switching limit timing violation. To resolve this for a 100 MHz PLB bus system, a second lower frequency bus will be added as follows:
  1. 1-Add a second PLB bus.
  2. 2-Using the Clock Wizard, connect a 50 MHz clock to the second PLB bus.
  3. 3-In the Clock Wizard, use the "Set Clock Relationships?" button to group the 50 MHz clock with the 100 MHz PLB clock (MicroBlaze clock).
  4. 4-Add a PLB to PLB Bridge.
  5. 5-On the PLB to PLB Bridge, connect the MPLB to the second PLB bus; connect the SPLB to the main PLB bus.
  6. 6-Configure the PLB to PLB Bridge: Set the SPLB "Bus Clock Ratio" to 2. This allows the second PLB bus to run at a 1:2 ratio of the main PLB bus speed.
  7. 7-Connect the 50 MHz clock to both the System Monitor IP and the second PLB bus.
  8. 8-Connect the system reset to the second PLB bus.
  9. 9-Connect the Processor System Reset "Slowest_sync_clk" to the 50 MHz clock.
  10. 10-Set the address ranges for the PLB to PLB Bridge; all other addresses can remain the same. The PLB to PLB Bridge parameters, "C_RNG0_BASEADDR" and "C_RNG0_HIGHADDR", should match the xps_sysmon_adc address range. Below are the address ranges used in the 12.4 ML605 BIST design from the MHS file:

    BEGIN plbv46_plbv46_bridge
    PARAMETER INSTANCE = plbv46_plbv46_bridge_0
    PARAMETER HW_VER = 1.03.a
    PARAMETER C_BRIDGE_BASEADDR = 0x86200000
    PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
    PARAMETER C_NUM_ADDR_RNG = 1
    PARAMETER C_RNG0_BASEADDR = 0x83800000
    PARAMETER C_RNG0_HIGHADDR = 0x8380ffff
    PARAMETER C_BUS_CLOCK_RATIO = 2
    BUS_INTERFACE MPLB = plb_v46_0
    BUS_INTERFACE SPLB = mb_plb
    END

For PLB bus speeds in excess of 160 MHz, the PLB to PLB bus "Bus Clock Ratio" can be set to 4 and the second PLB bus speed adjusted at a 1:4 ratio.
AR# 38817
创建日期 10/29/2010
Last Updated 12/02/2010
状态 Active
Type 已知问题
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
Tools
  • EDK - 12.1
  • EDK - 12.2
  • EDK - 12.3
IP
  • XPS SYSMON Analog Digital Converter (ADC)
  • AXI System Monitor