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AR# 38851

SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected


In v7.2 of the SPI-3 Link Layer core, the monitoring logic is not connected up in the simulation testbench. The monitoring logic checks that the data input to the rx interface matches the loopedback tx data available at the output. This affects all supported device families.


This issue has been fixed in v7.2rev1 of the core available as a patch for download; see (Xilinx Answer 35141).



Answer Number 问答标题 问题版本 已解决问题的版本
35141 SPI-3 Link Layer v7.2 — ISE Design Suite 12.1 的版本说明和已知问题 N/A N/A
AR# 38851
创建日期 11/05/2010
Last Updated 05/23/2014
状态 Archive
Type 综合文章
  • SPI-3 Link Layer Interface, Multi-channel