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AR# 38864

MIG v3.0-3.5, Spartan-6 MCB - Reset logic is incorrect for VHDL version

Description

For MIG 3.5 and older versions, the reset logic in the "mcb_soft_calibration.vhd" module for Spartan-6 FPGA controllers is incorrect.The Verilog version does not exhibit this problem. MIG 3.6 and newer versionshave the correct reset logic for VHDL and Verilog versions of the core.

解决方案

In MIG rev 3.5 and older versions,the logic for the reset register RST_reg in "mcb_soft_calibration.vhd" is incorrect.Following is the section of the VHDL code that needs to be modified.

Original VHDL Code:
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '0'; ---------------------------incorrectly assigns '0' to RST_reg----------------------------
else
RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;


Modified VHDL Code:
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '1';
else
RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;

AR# 38864
创建日期 11/05/2010
Last Updated 12/15/2012
状态 Active
Type 综合文章
器件
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG