After adding ChipScope Pro analyzer cores in the design, the following error occurs during MAP process:
"ERROR:Pack:2811 - Directed packing was unable to obey the user designconstraints
(MACRONAME=u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_USE_RPM_NE0.U_GAND_SRL_SET_MSET, RLOC=X0Y10) which requires the combination of the symbols listed below to be packed into a single SLICEM component.
The directed pack was not possible because: The top reasons for failure were:
-> A legal placement was never found for shift register symbol"u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[10].U_GAND_SRL_SLICE/U_SRLA".
......
The symbols involved are:
MuxCY symbol
"u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[10].U_GAND_SRL_SLICE/U_MUXA" (Output Signal = u_chipscope_ila/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_CS_GAND.U_CS_GAND_SRL/I_V5.U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[10].U_GAND_SRL_SLICE/U_MUXA/O)
...... "
The error indicates that MAP is not able to obey the RPM (RLOC) constraints embedded in the ChipScope Pro ILA netlist. The possible causes of this error are listed below: