Make a local copy of the XPS_LL_TEMAC core. 2.Edit the xps_ll_temac_v2_03_a\hdl\vhdl\v6_temac_wrap.vhd in the text editor and make the following changes:
port map ( -- 125MHz clock output from transceiver CLK125_OUT => clk125_o, -- out std_logic;
到
port map ( -- 125MHz clock output from transceiver CLK125_OUT => open, -- out std_logic;
从
port map ( -- 125MHz clock output from transceiver CLK125_OUT => clk125_o, -- out std_logic;
到
port map ( -- 125MHz clock output from transceiver CLK125_OUT => open, -- out std_logic;
Save the changes. 4.Clean the generated files and reimplement the design.