AR# 38890

描述











解决方案


To work around this error:

Make a local copy of the XPS_LL_TEMAC core.
2.Edit the xps_ll_temac_v2_03_a\hdl\vhdl\v6_temac_wrap.vhd in the text editor and make the following changes:




port map (
      -- 125MHz clock output from transceiver
      CLK125_OUT                => clk125_o,              -- out std_logic;



port map (
      -- 125MHz clock output from transceiver
      CLK125_OUT                => open,              -- out std_logic;     





 port map (
      -- 125MHz clock output from transceiver
      CLK125_OUT                => clk125_o,              -- out std_logic;    



port map (
      -- 125MHz clock output from transceiver
      CLK125_OUT                => open,              -- out std_logic;   

Save the changes.
4.Clean the generated files and reimplement the design. 
AR# 38890
日期 06/08/2020
状态 活跃
Type 已知问题
器件 More Less
Tools
IP