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AR# 38896

PlanAhead for Partial Reconfiguration - Incorrect PRCC #1 DRC Errors.


Doing a Partial Reconfiguration design for a Virtex-5 or Virtex-6 devices, I get the following DRC error.

PRCC #1 Reconfigurable module Inst_lots_o_flops has 12 clocks. Only 8 clocks are supported for the module. You need to floorplan so that the module has at most 8 clocks. Here is the list of global clocks inside the module: clk_buf_generate[0].BUFG_inst, clk_buf_generate[4].BUFG_inst, clk_buf_generate[5].BUFG_inst, clk_buf_generate[9].BUFG_inst, clk_buf_generate[10].BUFG_inst, clk_buf_generate[8].BUFG_inst, clk_buf_generate[11].BUFG_inst, clk_buf_generate[6].BUFG_inst, clk_buf_generate[7].BUFG_inst, clk_buf_generate[2].BUFG_inst, clk_buf_generate[1].BUFG_inst, clk_buf_generate[3].BUFG_inst.

Virtex-5 and Virtex-6 FPGA have 10 and 12 clock spines per region, respectively, so this message seems incorrect. Can it be ignored?


As long as your design has as many clock spines per region as it has driving the RP, you can safely ignore this error.

This will be fixed in a future version of the PlanAhead tool.
AR# 38896
日期 12/08/2011
状态 Active
Type ??????
  • PlanAhead - 12.1
  • PlanAhead - 12.2
  • PlanAhead - 12.3