AR# 38939

MIG v3.6-v3.61 Virtex-6 DDR3 - Debug signals to decrement Phase Detector IODELAY taps is wired incorrectly

The debug signal "dbg_pd_dec_dqs" should decrement Phase Detector IODELAY taps in memc_ui_top.v/.vhd

However it is incorrectly wired to increment.

The following shows the incorrect connection of "dbg_pd_dec_dqs":

.dbg_pd_inc_dqs (dbg_inc_rd_dqs),

.dbg_pd_dec_dqs (dbg_inc_rd_dqs),

The correct connection is:

.dbg_pd_inc_dqs (dbg_inc_rd_dqs),

.dbg_pd_dec_dqs (dbg_dec_rd_dqs),

This issue is fixed in the ISE 13.1 MIG v3.7 software release.

本答复记录是否对您有帮助？

Answer Number	问答标题	问题版本	已解决问题的版本
38951	MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2	N/A	N/A

AR# 38939
日期	08/20/2014
状态	Active
Type	综合文章
器件	Virtex-6 CXT Virtex-6 HXT Virtex-6 LX More Virtex-6 LXT Virtex-6 SXT Less
IP	MIG

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