AR# 38940


MIG v3.6 Virtex-6 QDRII+ - Import UCF does not import the clock signals.


When generating a new MIG v3.6 Virtex-6 FPGA QDRII+ design using the Fixed Pinout selection and the Import UCF feature, the clock signals may not be imported correctly and those valid pin locations may not be available to select.


If this occurs, select one of the available site locations and generate the design.

Then, open the *.ucf file that contains your generated pinout and manually change the clock pinout.

This is fixed in the ISE 13.1 MIG v3.7 software release.



Answer Number 问答标题 问题版本 已解决问题的版本
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 38940
日期 08/20/2014
状态 Archive
Type 综合文章
器件 More Less
People Also Viewed