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AR# 38940

MIG v3.6 Virtex-6 QDRII+ - Import UCF does not import the clock signals.

Description

When generating a new MIG v3.6 Virtex-6 FPGA QDRII+ design using the Fixed Pinout selection and the Import UCF feature, the clock signals may not be imported correctly and those valid pin locations may not be available to select.

解决方案

If this occurs, select one of the available site locations and generate the design.

Then, open the *.ucf file that contains your generated pinout and manually change the clock pinout.

This is fixed in the ISE 13.1 MIG v3.7 software release.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 38940
创建日期 11/05/2010
Last Updated 08/20/2014
状态 Active
Type 综合文章
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG