AR# 38956


Aurora 8B10B v5.2 & v6.1 - Clock correction is disabled in the example design


Why do I never see clock correction sequences transmitted when I use the example design?


The example design incorrectly keeps the standard_cc_module module in reset due to the incorrect polarity of the lane_up_reduce_i signal. If you invert the lane_up_reduce_i signal in the example_design module before it goes to the standard_cc_module module, this will resolve your issue.
AR# 38956
日期 03/01/2013
状态 Active
Type 综合文章
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