If operating with an input voltage that exceeds the Input Voltage Spec (Vin) for a Virtex-4 or Virtex-5 device, there is a small leakage path from theP to N pin regardless of how the pair is configured.
For example, if a pair of pins is configured as LVCMOS_25 inputs, and the P pin has a 10K pull-up while the N pin is being driven, such that there is significant negative voltage, then the P pin might see the pull-up level drop due to uAs of leakage from P to N.
The user I/O pins for the Virtex-4, Virtex-5, and Virtex-6device families can be used as differential pin pairs.Between the two pins of every differential pin pair, there is a programmable circuit that behaves like a differential termination resistor. This circuit can be enabled in differential signalingapplications using the DIFF_TERM attribute, but is otherwise disabled.
When one pin of a differential pair interfaces with voltages that fall outside the Vin specification from the recommended operating conditions of the family data sheet, there can be a small amount of leakage between the pair regardless of the configuration of the I/Os.If operating within the data sheet specifications, the Pin Leakage (IL) does not violate the specification.
To avoid excessive leakage: