AR# 39046

Spartan-6 IODELAY2 - Late Data Edge and Early Data Edge Timing Analysis

描述

This Answer Record describes how to use timing constraintsto account for theearly data edge delay andlate data edge delayIODELAY2 errata issue, as noted in (Xilinx Answer 38408)

解决方案


Late Data Edge Delay Timing Analysis
In the case with the IDELAY in the data path, reduce the OFFSET IN requirement by the 350ps to compensate for the lack of support by the timing tools to included this additional data path delay in the setup analysis:
#base constraints:
NET "Clock_In" TNM_NET = Clock_In;
TIMESPEC TS_Clock_In = PERIOD "Clock_In" 5 ns HIGH 50%;
#original constraint:
NET "Data_In" OFFSET = IN 4.00 ns VALID 5 ns BEFORE "Clock_In";
#modified constraint:
NET "Data_In" OFFSET = IN 3.65 ns VALID 5 ns BEFORE "Clock_In"; #Subtracted the 350ps from 4ns
In the case with the IDELAY in the clock path, increase the OFFSET IN requirement by the 350ps to compensate for the lack of support by the timing tools to included this additional clock path delay in the hold analysis:
#base constraints:
NET "Clock_In" TNM_NET = Clock_In;
TIMESPEC TS_Clock_In = PERIOD "Clock_In" 5 ns HIGH 50%;
#original constraint:
NET "Data_In" OFFSET = IN 4.00 ns VALID 5 ns BEFORE "Clock_In";
#modified constraint:
NET "Data_In" OFFSET = IN 4.35 ns VALID 5 ns BEFORE "Clock_In"; #Add the 350ps to 4ns, to move the hold time
*In the case where an ODELAY is used, change the OFFSET IN to an OFFSET OUT, and the rest of the rules apply the same.
Early Edge Delay Timing Analysis
In the case of Early Edge Delay timing analysis (only seen in ODELAY mode), increase the OFFSETOUT requirement by 350ps(if IODELAY2 is used onthe data path), and reduce the OFFSETOUT requirement by 350ps(if IODELAY2 is used onthe clock path).This is opposite of what is done for the Late Data Edge Delay above.

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AR# 39046
日期 12/15/2012
状态 Active
Type 综合文章
器件