UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39063

Spartan-6 FPGA Integrated Block for PCI Express - Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts?

描述

Version Found: v1.1; v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).

The Spartan-6 FPGA Integrated Block User Guide says trn_reset_n/user_reset_out(AXI) should be asserted at the same time as sys_reset_n. However, during simulation, at time zero when sys_reset_n is asserted, trn_reset_n/user_reset_out(AXI) does not assert for approximatelyfour microseconds (this also occurs in hardware).

解决方案

This difference occurs only at startup (time 0) and is due to logic within the block that ensures no contention is on the outputs during configuration. After initial startup, any further assertions of sys_reset_n cause trn_reset_n/user_reset_out(AXI) to assert simultaneously. This behavior is expected.

Revision History
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Updated for v2.3
12/11/2010 - Initial release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
37939 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1 N/A N/A

相关答复记录

AR# 39063
日期 12/15/2012
状态 Active
Type 综合文章
器件
IP
的页面