AR# 39067


MIG Virtex-6 DDR2 - Why am I unable to select BUFIO pins in the dropdown list when creating a DDR2 MIG v3.6 design with AXI interface enabled?


When creating a DDR2 MIG design with the AXI interface enabled and after importing my pre-fixed pinouts, I cannot select the BUFIO:0 and BUFIO:1pins in the MIG GUI, or any resources. If I assign the BUFIO:0 and BUFIO:1pins manually, the following error displays without the BUFIO recommendations:

"ERROR: BUFIO Constraint for the Capture Clock - "gen_ck_cpt[0]" is not provided or provided BUFIO constraint is invalid. Following is (are) the valid BUFIO Constraints for this Capture Clock. But verify whether any of these IOB sites are utilized by any other constraints or Pin LOC's."

How can I solve this issue?

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The BUFIO placement requires that each DQS group in a bankbe associated with a CC-P pin reserved for BUFIO. Based onthe pin selection for DQ, DQS/DQS#, addr, the control signals, and so on, there might not be any CC-P pins available to choose from.

Please check the pinouts carefully and make sure that there are valid sites to reserve for BUFIO and BUFR. The error messageshould have stated more clearly that no CC-P sites are available to select for BUFIO and BUFR.



Answer Number 问答标题 问题版本 已解决问题的版本
34308 MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met N/A N/A
AR# 39067
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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