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General Description: What is the usage of GSR_SIGNAL, GR_SIGNAL, PRLD_SIGNAL, and GTS_SIGNAL text macros in Verilog simulation?
In Alliance 1.4 and 1.5i, the general procedure for specifying global signals for Verilog simulation flow involves defining the global signals with one of the following text macros: GSR_SIGNAL, GR_SIGNAL, PRLD_SIGNAL, or GTS_SIGNAL. This is necessary because these global nets do not exist as external ports in the UNISIM/SIMPRIMS libraries; as a result, the reset of the UNISIMS/SIMPRIMS components is controlled by the detection of the text macros. In addition, you must declare the global signal either as a Verilog wire or reg. Your choice of wire or reg depends on whether your design contains a STARTUP component.
The global 3-state signal is defined using the Verilog macro, GTS_SIGNAL. However, this is not defined in the UNISIM models.