We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3915

V1.4.0 COREGEN: 30-bit bus input width limit on COREGEN modules / Cannot specify 32-bit input bus widths / integer arithmetic overflow


Keywords: coregen, bus, input, bit, limit

Urgency: standard

General Description:
Currently many of the COREGEN modules are limited to 30-bit
bus input widths.


The reason why many of the modules delivered with COREGen
v1.4.x are limited to bus widths of 31 or less is
because of the way arithmetic operations are implemented in
the VHDL behavioral models. Most models convert incoming
operands from their binary (bit_vector) representations to
integers, perform any necessary arithmetic using the standard
set of VHDL arithmetic operators, and convert the results back
to bit_vectors for expression at the output ports.
Unfortunately, VHDL's integer datatype is restricted to
numbers in the range -2^31 to 2^31. As a result, the above
process can fail when busses with bit-widths over 31 bits
contain numbers outside this range.

The planned solution is to re-implement the behavioral models
using bit-wise arithmetic instead of integer arithmetic, since
bit-wise arithmetic places no limit on bit width.
Approximately 75% of the affected models will be corrected in
the upcoming COREGen v1.5 release. For these modules, the
parameter ranges will be expanded to include 32-bits.

AR# 3915
创建日期 05/14/1998
Last Updated 03/12/2000
状态 Archive
Type 综合文章